library verilog;
use verilog.vl_types.all;
entity uart_receiver is
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        clken_16bps     : in     vl_logic;
        rxd             : in     vl_logic;
        rxd_data        : out    vl_logic_vector(7 downto 0);
        rxd_flag        : out    vl_logic
    );
end uart_receiver;
